TSMC Brings Patented Packaging Technology to Altera's 20nm Chips

Taiwan Semiconductor Manufacturing Co. (TSMC), world's major pure foundry, and Altera Corp., a world leading vendor of programmable chips, have announced cooperation to bring TSMC's patented, fine-pitch copper bump-based packaging technology to Altera's 20nm Arria 10 FPGAs and SoCs.

Altera is the first company to adopt this technology in commercial production to deliver improved quality, reliability and performance to Altera's 20nm device family.

According to Altera executives, TSMC's flip chip BGA package technology provides Arria 10 devices with better quality and reliability than standard copper bumping solutions through the use of fine-pitch copper bumps.

They say that the technology can  accommodate very high bump counts as required by high-performance FPGA products. Also, it provides excellent bump joint fatigue life, improved performance in electro-migration current and low stress on the ELK (Extra Low-K) layers, all highly critical features for products employing advanced silicon technologies.

TSMC's copper bump-based package technology is scalable and ideal for products that feature large die size and small bump pitch. It includes a DFM/DFR implementation from TSMC that adjusts package design and structure for wider assembly process windows and higher reliability. The technology has demonstrated better than 99.8% production  yields.

Altera is shipping Arria 10 FPGAs based on TSMC 20SoC process technology and featuring this innovative packaging technology. Arria 10 FPGAs and SoCs provide the FPGA industry's highest density in a single monolithic die and up to 40% lower power than the previous 28nm Arria family.

Bill Mazotti, vice president of worldwide operations and engineering at Altera, says that the TSMC technology is a great complement to Arria 10 FPGAs and SoCs and helps the company address the packaging challenges at the 20nm node. (KL)