Taipei, March 27, 2008 (CENS)--Taiwan Semiconductor Manufacturing Co. (TSMC) this Monday (Mar.24) introduced 40nm manufacturing process technology, becoming the first silicon-foundry supplier in the world to unveil the technology that shrinks geometry of circuits on chips to only 40 nanometers.

Industry watchers expect Qualcomm, Nvidia, AMD-ATI and Altera to begin using the process next quarter.

TSMC states in a new release that the new process node supports a performance-driven general-purpose technology, codenamed 40G, and a power-efficient low power technology, dubbed as 40LP. It features a full design service package and a design ecosystem that covers verified third-party IP, third-party EDA tools, TSMC-generated SPICE models and foundation IPs.

The 40nm node features manufacturing innovations that enable its LP and G processes to deliver 2.35 folds the raw gate density that 65nm process offers, an improvement from 45nm technology`s two folds the density offered by 65nm process.

TSMC develops 40LP for leakage-sensitive applications such as wireless and portable devices and 40G for performance applications including CPU, GPU (graphic processing unit), game console, networking and FPGA designs and other high-performance consumer devices.

The transition from 45nm to 40nm low power technology reduces power consumption up to 15%. TSMC introduced 45nm process last year.

The 40nm process employs a combination of 193nm immersion photolithography and extreme low-k (ELK) material. The logic family includes a low-power triple gate oxide (LPG) option to support high performance wireless and portable applications. Both the G and the LP processes offer multiple Vt core devices and 1.8V, 2.5V I/O options to meet different product requirements.

Some institutional investors pointed out TSMC had led industrial peers by at least two fiscal quarters in sub-45nm process technology.

(by Ken Liu)