Unable to significantly break through a bottleneck in the technical development of the key photolithography in the 32-nanometer-and-below production process, semiconductor makers worldwide have been eager to seek new alternative solutions in packaging technologies, resulting in a delay of their upgrading the 32-nano and below process.
Recently, at the International Microsystems, Packaging, Assembly and Circuits Technology (IMPACT) Conference 2007, which took place in Taipei from Oct.1 to 3, quite a few attendees reached a consensus that 3D packaging technologies will become the mainstream solutions in the future.
However, the hottest packaging solution at the conference was a 3D through-silicone via (TSV) technology, which has been developed among the world`s leading suppliers in the sector, including IBM, Samsung, Taiwan Semiconductor Manufacturing Co., Ltd. and Advanced Semiconductor Engineering Inc.
In fact, large suppliers of photolithography devices, ASML and Belgium`s Interuniversity Microelectronics Centre have collectively succeeded in developing a machine using extreme ultraviolet (EUV) to turn out 12-inch wafers through the 32-nano process.
Nevertheless, many semiconductor makers in Taiwan still prefer using the existing immersion devices to produce 32-nano chips while continuing to improve production processes, and at the same time keep looking for better solutions, instead of resorting to the EUV-based device. It is because the EUV-based device is exceedingly expensive, which also goes for investing in the 32-nano and below process, which costs usually three to four folds more than the 90-nano process.
Moore`s Law
Perhaps the primary motivation driving the global makers of semiconductors to upgrade their packaging technologies is "Moore`s Law," which was introduced by one of Intel`s founders, Moore Gordon, in 1965 and says that the number of chips embedded on an integrated circuit (IC) would double every two years, hence improving IC performance but lowering their prices every two years. So a fleeting two-year period has become the magic time span clocking rapid advancement in high-tech products, as well as obliging suppliers in the sector to upgrade production technology over the same brief period.
In recent years, many top-selling mobile phones feature low prices and multi-functionality, making system-on-a-chip applications popular. The world`s leading IC makers, such as Qualcomm International Inc. and Texas Instruments Inc., have already moved to use 65- or 45-nano processes to produce chips incorporating all the functions for a handset, as well as considering to adopt 3D packaging technologies.
As IBM and Samsung have succeeded in applying the 3D TSV technologies in manufacturing ICs or high-capacity memories at low cost this year, it means that 3D packaging technologies have become mature, and are regarded as the most important element to sustain the industry in the next five years.
Insiders noted that the 3D TSV technology is able to reduce the power consumption of a processor by 20% relative to others, enabling chip makers to stack passive components, memory, logic ICs and analog ICs into a single chip, which cuts the time spent on chip design.
Besides, 3D TSV also allows suppliers to interconnect a central processing unit (CPU) with SARM at speedy bandwidths. Thus, a CPU processed through 3D TSV needs not be embedded with flash memory, which usually occupies a large area in a CPU, enabling the production of more compact items.
New Demands for 3D Packaging
Generally speaking, 3D packaging technologies were born in 2000, when some packaging companies and integrated device manufacturers started applying related techniques in production, but did not become popular because makers of semiconductors concentrated on developing system-on-a-chip technologies at the time.
Nevertheless, as demands for Bluetooth chips, wireless local area network (WLAN) chips, radio on chips (RoCs), baseband chips and complementary metal oxide semiconductor (CMOS) image sensors have exploded over the past two years, the issue of the relevance of 3D packaging technologies has again become center-stage, especially for globally well-known chip makers such as Qualcomm, Broadcom Corporation, Intel and Advanced Micro Devices Inc (AMD).
Having won big orders from the aforementioned chipmakers, Taiwan`s Advanced Semiconductor, Siliconware Precision Industries Co. Ltd. and Kinsus Interconnect Technology Corp., who all have been engaged in developing 3D packaging technologies for more than 5 years, are poised to become the biggest winners in the race to build alternative solutions of new packaging approaches.
For instance, Advanced Semiconductor and its reinvested company Universal Scientific Industry Co., Ltd. applies 3D packaging technologies in developing and mass producing mini WLAN modules, which have reportedly been adopted by Apple in its iPod Touch.
Meanwhile, Siliconware and Advanced Semiconductor have won orders from big enterprises in the sector for packaging NAND memory cards, Bluetooth modules and CMOS image sensor modules. Also, Kinsus, Taiwan`s largest supplier of substrates made of bismaleimide triazine (BT), which are packaging substrates mainly used by packaging companies, has reaped bountiful profits from the availability of new packaging technologies.
The market for consumer electronics like mobile phones and portable devices grows rapidly, so has the demand for new packaging technologies in the semiconductor making industry. An annual compound growth rate in the semiconductor packaging industry is expected to go up to 16%.
In addition, 3D packaging is already well-developed and able to create economy-of-scale in production quickly, providing packaging companies a chance to outpace wafer suppliers, according to Goldman Sachs.
Processing Capacity of Stacking and Packaging Companies Unit: One million Chips |
| | 2004 | 2005 | 2006 | 2007 | 2008 |
Stacking | 790 | 966 | 1,171 | 1,349 | 1,519 |
Packaging | 732 | 927 | 1,104 | 1,280 | 1,408 |
(by Steve Chuang)
